1. Filed of the Invention
The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit including a multi-input logic circuit constituted by a plurality of voltage-activated transistors which are connected in series, and a method of manufacturing such a semiconductor integrated circuit.
2. Description of the Related Art
Generally, a multi-input logic circuit such as a NAND or NOR circuit comprises a plurality of n-channel and p-channel MOSFETs (metal oxide semiconductor field effect transistors) which are electrically connected in series between a power supply terminal and a grounding terminal. Referring to FIG. 16 of the accompanying drawings, a 2-input NAND circuit comprises n-channel MOSFETs 100 and 101 electrically connected in series between a grounding power supply terminal Vss and a signal output terminal Pout, and p-channel MOSFETs 102 and 103 electrically connected in parallel between a circuit operation voltage terminal Vcc and the signal output terminal Pout. Gate electrodes of the n-channel MOSFET 100 and p-channel MOSFET 102 are electrically connected to a signal input terminal Pin2 while gate electrodes of the n-channel MOSFET 101 and p channel MOSFET 103 are connected to a signal input terminal Pin1.
When this 2-input NAND circuit is constituted by a bulk-type element in which the n-channel MOSFETs 100, 101 and the p-channel MOSFETs 102, 103 are formed on a main surface of a silicon single crystal substrate, a threshold voltage is increased in the n-channel MOSFET 101 at the output terminal Pout due to a body effect. The increase of the threshold voltage adversely affects the current-activated performance of the 2-input NAND circuit, and lowers the overall operation speed of the semiconductor integrated circuit.
The use of the SOI (silicon on insulator) or SOS (silicon on sapphire) structure is effective in reducing the body effect in the semiconductor integrated circuit. In the SOI structure, an SOI substrate includes a silicon single crystal layer which is formed on a silicon single crystal substrate via an insulator, and elements are mounted on the silicon single crystal layer. With the SOS structure, an SOS substrate is provided with a silicon single crystal layer which is formed on a sapphire substrate, and elements are mounted on the silicon single crystal layer. In either structure, the elements are isolated, and potentials of body regions depend upon a built-in potential between the body region and a source region. Therefore, it has been expected that the increase of the threshold voltage due to the body effect can be prevented in the n channel MOSFET 101 of the 2-input NAND circuit.
However, the logic circuit including the foregoing SOI elements suffers from variations of element characteristics due to a varying body potential (substrate bias effect), and a reduced noise margin. As a result, each SOI element needs a body contact. If the body contacts are provided for the SOI elements in a structure identical to that of existing bulk-type elements, it is not possible to reduce the body effect. As a result, the operation speed of the semiconductor integrated circuit will be lowered.
According to a first feature of the invention, there is provided a semiconductor integrated circuit comprising: a substrate having an insulator at least on a surface thereof; a semiconductor layer on the insulator; and at least first and second of voltage-activated transistors having the same channel conduction type, electrically connected between a power supply terminal and an output terminal in the semiconductor layer and having a body region which is electrically isolated; wherein a source region and the body region of at least the first or second voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential.
In accordance with a second feature of the invention, there is provided a semiconductor integrated circuit comprising: a substrate having an insulator at least on a surface thereof, a semiconductor layer on the insulator; a first voltage-activated transistor including a source region connected to a power supply terminal and a body region and a drain region in the semiconductor layer; a second voltage-activated transistor which includes in the semiconductor layer, a source region which is integral with the drain region of the first voltage-activated transistor, a body region having the same conduction type as that of the body region of the first voltage-activated transistor and electrically isolated from the body region of the first voltage-activated transistor, a drain region electrically connected to an output terminal, and a body contact region which is integral with the body region of at least the second voltage-activated transistor, has the same conduction type as that of the body region of at least the second voltage-activated transistor, has an impurity concentration higher than that of the body region, and is positioned along the gate width; and a wiring electrically connecting the source region and the body contact region of the second voltage-activated transistor, extending from the source region along the gate width and bent in the shape of L along the gate length.
With a third feature of the invention, there is provided a semiconductor integrated circuit comprising: a substrate having an insulator at least on a surface thereof; a semiconductor layer on the insulator; a plurality of first voltage-activated transistors having the same channel conduction type, electrically connected in parallel or in series between a first power supply terminal and an output terminal in the semiconductor layer and having body regions which are electrically isolated; and a plurality of second voltage-activated transistors having the same channel conduction type, electrically connected in series or in parallel to a second power supply terminal and the output terminal in the semiconductor layer and having body regions which are electrically isolated, wherein a source region and the body region of at least the first or second voltage-activated transistor connected in series to the output terminal are electrically connected and have substantially the same potential.
According to a fourth feature of the invention, there is provided a semiconductor integrated circuit comprising: a substrate having an insulator at least on a surface thereof; a semiconductor layer on the insulator; a first voltage-activated transistor which has a first source region, a first body region and a first drain region in the semiconductor layer; a second voltage-activated transistor which has a second source or drain region integral with the first source or drain region, a second body region having the same channel conduction type as that of the first body region and electrically isolated therefrom, and a second drain or source region, the second voltage-activated transistor arranged along the gate length of the first voltage-activated transistor, in the semiconductor layer; a first body contact region which has the same conduction type as that of the second body region, is integral with the second body region in the semiconductor layer, has an impurity concentration higher than that of the second body region, the first body contact region positioned along the gate width; a first wiring electrically connecting a second source region and the first body contact region of the second voltage-activated transistor, extending from the second source region along the gate width and bent in the shape of L toward the first body contact region along the gate length; a third voltage-activated transistor including a third source region, a third body region which has a conduction type opposite to those of the first and second body regions, and a third drain region, in the semiconductor layer, the third voltage-activated transistor being axi-symmetrical to the first voltage-activated transistor along the gate width of the first voltage-activated transistor; a fourth voltage activated transistor including a fourth source or drain region integral with the third source or drain region, a fourth body region having the same conduction type as that of the third body region and electrically isolated therefrom, and a fourth drain or source region, in the semiconductor layer, the fourth voltage-activated transistor positioned along the gate length of the third voltage-activated transistor; a second body contact region which has the conduction type same as that of the fourth body region, is integral with the fourth body region in the semiconductor layer, and has an impurity concentration higher than that of the fourth body region, the second body contact region positioned along the gate width and being axi-symmetrical to the first body contact region; and a second wiring electrically connecting a fourth source region and the second body contact region of the fourth voltage-activated transistor, extending from the fourth source region along the gate width and bent in the shape of L toward the second body contact region along the gate length.
According to a fifth feature of the invention, a semiconductor integrated circuit comprises: a substrate having an insulator at least on a surface thereof; a semiconductor layer on the insulator; and at least first and second voltage-activated transistors which are electrically connected in series between a first power supply terminal and a second power supply terminal, of which potential is higher than that of the first power supply terminal, in the semiconductor layer and include electrically isolated body regions, wherein a source region and a body region of at least the first or second voltage-activated transistor near the second power supply terminal are electrically connected and have substantially the same potential.
With a sixth feature of the invention, a method of manufacturing a semiconductor integrated circuit comprises: forming a plurality of voltage-activated transistors in a semiconductor layer on a substrate having an insulator at least on a surface thereof, the voltage-activated transistors including body contact regions electrically connecting a body region and a source region and having the same channel conduction type; and electrically connecting the voltage-activated transistors in series to a power supply terminal and an output terminal, and a source region and the body contact region of at least the voltage-activated transistor near the output terminal.
Finally, a seventh feature of the invention, a method of manufacturing a semiconductor integrated circuit comprising: storing a cell library in a database, the cell library containing data of at least a plurality of voltage-activated transistors electrically connected in series and in which a body region and a source region of at least the voltage-activated transistor near an output terminal are electrically connected and have the same potential; designing a logic circuit; locating the cell library from the database to a memory space on the basis of the logic circuit by using a design automation system; linking the cell library in the memory space using the design automation system and creating logic circuit data; making a manufacturing mask on the basis of the logic circuit data created by the design automation system; and forming a logic circuit in a semiconductor layer on a substrate having an insulator at least on a surface thereof and manufacturing a semiconductor integrated circuit.